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sci-electronics/yosys: new package, add 0.32, 0.40
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
parent
239efc4602
commit
f756ce0042
4
sci-electronics/yosys/Manifest
Normal file
4
sci-electronics/yosys/Manifest
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@ -0,0 +1,4 @@
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DIST abc-0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz 6154902 BLAKE2B 1767891c9ae76aa0baea85a26a22dace92912affe857f9637abc90827b3193e2cf736e7b81cb2c3e56d80d76a98220863e0669fff5df9fa86ee4c990c594edd2 SHA512 7233edda97b6a2dfbb285b1884befc515b246392050cf01ae623c6bac4b4203cd667022f2fda21c068efc3d72a9fe50c3a66a2f16399fe959bea95f33e305f94
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DIST abc-bb64142b07794ee685494564471e67365a093710.tar.gz 6119314 BLAKE2B 6cba6362e59bb766d784a1c9edeca8906bf2b08df79d44a16ddb69c72c30e57c95a8375e0b0bad489c35a9a3728c1ccdd1b7fe84d5f5f48f113d59f7615aab8d SHA512 74d1c7c4b204fe30e85e31ed837feadbda9759afd9703ad525a1de53cb704d0f59ac25f78b918e3003fbc87b3afd293d138e0cfc1b38df9139a9aea8f5737fe7
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DIST yosys-0.32.tar.gz 2552341 BLAKE2B 491cd92de29097f3f9baca4c0982acc7fa180ae3b4ee5980b5246618520b3b0d53f0489615fba903838daef35b7a676106ef8b56e6f22ccc5e927429174dc4ac SHA512 3704ca8286e93ca53344b2a518ba4f2b9c137cf9688a95863f691cce3cca761d061100d3b93a0ad1dbabda13c0dbb137c5234abb6675ce2e5b5167701ccb0910
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DIST yosys-0.40.tar.gz 2802706 BLAKE2B d44a436b48bb0c65f67ee398a1663f309e169a22d1a55a0ac46ba60c6fbe9d60a31476e577c091c11bfec687491885df94db6ab6e6c135c014f813f9f7fb7811 SHA512 b42afbd9f4d65fe81110c0516e1d5d2cb8accc7fcc8f5bc79887d788547bab74292933b062405cf7c93c74311ad633a12c2ee11be55d7a803445dfac372937cd
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226
sci-electronics/yosys/files/yosys-0.31-abc-c++17-fix.patch
Normal file
226
sci-electronics/yosys/files/yosys-0.31-abc-c++17-fix.patch
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@ -0,0 +1,226 @@
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--- yosys-yosys-0.31/abc/src/misc/zlib/trees.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/misc/zlib/trees.c 2023-07-18 08:56:03.335795722 -0700
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@@ -1144,7 +1144,7 @@
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*/
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local unsigned bi_reverse(unsigned code, int len)
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{
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- register unsigned res = 0;
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+ unsigned res = 0;
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do {
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res |= code & 1;
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code >>= 1, res <<= 1;
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--- yosys-yosys-0.31/abc/src/misc/zlib/crc32.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/misc/zlib/crc32.c 2023-07-18 08:55:38.138798430 -0700
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@@ -269,8 +269,8 @@
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/* ========================================================================= */
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local unsigned long crc32_little(unsigned long crc, const unsigned char FAR *buf, unsigned len)
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{
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- register u4 c;
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- register const u4 FAR *buf4;
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+ u4 c;
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+ const u4 FAR *buf4;
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c = (u4)crc;
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c = ~c;
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@@ -306,8 +306,8 @@
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/* ========================================================================= */
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local unsigned long crc32_big(unsigned long crc, const unsigned char FAR *buf, unsigned len)
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{
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- register u4 c;
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- register const u4 FAR *buf4;
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+ u4 c;
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+ const u4 FAR *buf4;
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c = REV((u4)crc);
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c = ~c;
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--- yosys-yosys-0.31/abc/src/misc/zlib/deflate.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/misc/zlib/deflate.c 2023-07-18 08:55:10.870801362 -0700
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@@ -1027,9 +1027,9 @@
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local uInt longest_match(deflate_state *s, IPos cur_match)
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{
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unsigned chain_length = s->max_chain_length;/* max hash chain length */
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- register Bytef *scan = s->window + s->strstart; /* current string */
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- register Bytef *match; /* matched string */
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- register int len; /* length of current match */
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+ Bytef *scan = s->window + s->strstart; /* current string */
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+ Bytef *match; /* matched string */
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+ int len; /* length of current match */
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int best_len = s->prev_length; /* best match length so far */
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int nice_match = s->nice_match; /* stop if match long enough */
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IPos limit = s->strstart > (IPos)MAX_DIST(s) ?
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@@ -1044,13 +1044,13 @@
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/* Compare two bytes at a time. Note: this is not always beneficial.
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* Try with and without -DUNALIGNED_OK to check.
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*/
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- register Bytef *strend = s->window + s->strstart + MAX_MATCH - 1;
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- register ush scan_start = *(ushf*)scan;
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- register ush scan_end = *(ushf*)(scan+best_len-1);
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+ Bytef *strend = s->window + s->strstart + MAX_MATCH - 1;
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+ ush scan_start = *(ushf*)scan;
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+ ush scan_end = *(ushf*)(scan+best_len-1);
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#else
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- register Bytef *strend = s->window + s->strstart + MAX_MATCH;
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- register Byte scan_end1 = scan[best_len-1];
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- register Byte scan_end = scan[best_len];
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+ Bytef *strend = s->window + s->strstart + MAX_MATCH;
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+ Byte scan_end1 = scan[best_len-1];
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+ Byte scan_end = scan[best_len];
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#endif
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/* The code is optimized for HASH_BITS >= 8 and MAX_MATCH-2 multiple of 16.
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@@ -1173,10 +1173,10 @@
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*/
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local uInt longest_match(deflate_state *s, IPos cur_match)
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{
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- register Bytef *scan = s->window + s->strstart; /* current string */
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- register Bytef *match; /* matched string */
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- register int len; /* length of current match */
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- register Bytef *strend = s->window + s->strstart + MAX_MATCH;
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+ Bytef *scan = s->window + s->strstart; /* current string */
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+ Bytef *match; /* matched string */
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+ int len; /* length of current match */
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+ Bytef *strend = s->window + s->strstart + MAX_MATCH;
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/* The code is optimized for HASH_BITS >= 8 and MAX_MATCH-2 multiple of 16.
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* It is easy to get rid of this optimization if necessary.
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@@ -1261,8 +1261,8 @@
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*/
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local void fill_window(deflate_state *s)
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{
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- register unsigned n, m;
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- register Posf *p;
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+ unsigned n, m;
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+ Posf *p;
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unsigned more; /* Amount of free space at the end of the window. */
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uInt wsize = s->w_size;
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--- yosys-yosys-0.31/abc/src/misc/extra/extraUtilUtil.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/misc/extra/extraUtilUtil.c 2023-07-18 08:53:09.857814372 -0700
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@@ -97,8 +97,8 @@
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***********************************************************************/
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int Extra_UtilGetopt( int argc, char *argv[], const char *optstring )
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{
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- register int c;
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- register const char *place;
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+ int c;
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+ const char *place;
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globalUtilOptarg = NULL;
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--- yosys-yosys-0.31/abc/src/misc/bzlib/compress.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/misc/bzlib/compress.c 2023-07-18 08:54:26.994806079 -0700
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@@ -190,15 +190,15 @@
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zPend = 0;
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}
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{
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- register UChar rtmp;
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- register UChar* ryy_j;
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- register UChar rll_i;
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+ UChar rtmp;
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+ UChar* ryy_j;
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+ UChar rll_i;
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rtmp = yy[1];
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yy[1] = yy[0];
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ryy_j = &(yy[1]);
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rll_i = ll_i;
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while ( rll_i != rtmp ) {
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- register UChar rtmp2;
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+ UChar rtmp2;
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ryy_j++;
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rtmp2 = rtmp;
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rtmp = *ryy_j;
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@@ -360,8 +360,8 @@
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if (nGroups == 6 && 50 == ge-gs+1) {
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/*--- fast track the common case ---*/
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- register UInt32 cost01, cost23, cost45;
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- register UInt16 icv;
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+ UInt32 cost01, cost23, cost45;
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+ UInt16 icv;
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cost01 = cost23 = cost45 = 0;
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# define BZ_ITER(nn) \
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--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddSat.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddSat.c 2023-07-18 08:59:43.372772066 -0700
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@@ -279,7 +279,7 @@
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DdNode * f,
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int * length)
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{
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- register DdNode *F;
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+ DdNode *F;
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st__table *visited;
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DdNode *sol;
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cuddPathPair *rootPair;
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@@ -351,7 +351,7 @@
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DdNode * f,
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int * weight)
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{
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- register DdNode *F;
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+ DdNode *F;
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st__table *visited;
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cuddPathPair *my_pair;
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int complement, cost;
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--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddSplit.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddSplit.c 2023-07-18 08:59:42.987772107 -0700
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@@ -638,8 +638,8 @@
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{
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DdNode *N,*Nv,*Nnv;
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- register double min_v,min_nv;
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- register double min_N;
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+ double min_v,min_nv;
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+ double min_N;
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double *pmin;
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double *dummy;
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--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddCache.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddCache.c 2023-07-18 08:58:14.403781631 -0700
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@@ -229,7 +229,7 @@
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{
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int posn;
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unsigned hash;
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- register DdCache *entry;
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+ DdCache *entry;
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ptruint uf, ug, uh;
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ptruint ufc, ugc, uhc;
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@@ -283,7 +283,7 @@
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{
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int posn;
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unsigned hash;
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- register DdCache *entry;
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+ DdCache *entry;
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hash = ddCHash2_(op,cuddF2L(f),cuddF2L(g));
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// posn = ddCHash2(op,cuddF2L(f),cuddF2L(g),table->cacheShift);
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@@ -328,7 +328,7 @@
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{
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int posn;
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unsigned hash;
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- register DdCache *entry;
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+ DdCache *entry;
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hash = ddCHash2_(op,cuddF2L(f),cuddF2L(f));
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// posn = ddCHash2(op,cuddF2L(f),cuddF2L(f),table->cacheShift);
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--- yosys-yosys-0.31/abc/src/bdd/cudd/cuddBddIte.c 2023-06-28 02:10:24.000000000 -0700
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+++ yosys-yosys-0.31/abc/src/bdd/cudd/cuddBddIte.c 2023-07-18 08:58:13.834781692 -0700
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@@ -1203,8 +1203,8 @@
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unsigned int * topgp,
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unsigned int * tophp)
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{
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- register DdNode *F, *G, *H, *r, *f, *g, *h;
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- register unsigned int topf, topg, toph;
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+ DdNode *F, *G, *H, *r, *f, *g, *h;
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+ unsigned int topf, topg, toph;
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DdNode *one = dd->one;
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int comple, change;
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@@ -1305,7 +1305,7 @@
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unsigned int * topgp,
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unsigned int * tophp)
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{
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- register DdNode *r, *f, *g, *h;
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+ DdNode *r, *f, *g, *h;
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int comple, change;
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f = *fp;
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29
sci-electronics/yosys/metadata.xml
Normal file
29
sci-electronics/yosys/metadata.xml
Normal file
@ -0,0 +1,29 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE pkgmetadata SYSTEM "https://www.gentoo.org/dtd/metadata.dtd">
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<pkgmetadata>
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<maintainer type="person">
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<email>vowstar@gmail.com</email>
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<name>Huang Rui</name>
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</maintainer>
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<upstream>
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<remote-id type="github">YosysHQ/yosys</remote-id>
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</upstream>
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<longdescription lang="en">
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This is a framework for RTL synthesis tools. It currently has extensive
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Verilog-2005 support and provides a basic set of synthesis algorithms
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for various application domains.
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Yosys can be adapted to perform any synthesis job by combining the
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existing passes (algorithms) using synthesis scripts and adding
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additional passes as needed by extending the yosys C++ code base.
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Yosys is free software licensed under the ISC license (a GPL compatible
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license that is similar in terms to the MIT license or the 2-clause BSD
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license).
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</longdescription>
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<longdescription lang="zh">
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这是一个针对RTL合成工具的框架。它目前广泛支持Verilog-2005，并提供一套
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基础的合成算法用于多种应用领域。Yosys可以通过组合现有的合成脚本中的算法，
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并根据需要扩展Yosys的C++代码库来添加额外的算法，从而适应任何合成任务。
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Yosys是根据ISC许可证发布的免费软件，这是一种与GPL兼容的许可证，其条款与
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MIT许可证或二条款BSD许可证类似。
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</longdescription>
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</pkgmetadata>
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44
sci-electronics/yosys/yosys-0.32.ebuild
Normal file
44
sci-electronics/yosys/yosys-0.32.ebuild
Normal file
@ -0,0 +1,44 @@
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# Copyright 1999-2024 Gentoo Authors
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EAPI=8
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# get the current value from the yosys makefile...look for ABCREV
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ABC_GIT_COMMIT=bb64142b07794ee685494564471e67365a093710
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DESCRIPTION="framework for Verilog RTL synthesis"
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HOMEPAGE="http://www.clifford.at/yosys/"
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SRC_URI="
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https://github.com/YosysHQ/${PN}/archive/${P}.tar.gz
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https://github.com/YosysHQ/abc/archive/${ABC_GIT_COMMIT}.tar.gz -> abc-${ABC_GIT_COMMIT}.tar.gz
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"
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S="${WORKDIR}/${PN}-${PN}-${PV}"
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LICENSE="ISC"
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SLOT="0"
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KEYWORDS="~amd64"
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RDEPEND="
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dev-libs/boost
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media-gfx/xdot
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sys-devel/clang
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"
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DEPEND="${RDEPEND}"
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BDEPEND="dev-vcs/git"
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PATCHES=(
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"${FILESDIR}/${PN}-0.31-abc-c++17-fix.patch"
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)
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QA_PRESTRIPPED="
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/usr/bin/yosys-filterlib
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/usr/bin/yosys-abc
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"
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src_prepare() {
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mv "${WORKDIR}/abc-${ABC_GIT_COMMIT}" "${S}"/abc || die
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default
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}
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src_install() {
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emake DESTDIR="${D}" PREFIX='/usr' install
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}
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40
sci-electronics/yosys/yosys-0.40.ebuild
Normal file
40
sci-electronics/yosys/yosys-0.40.ebuild
Normal file
@ -0,0 +1,40 @@
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# Copyright 1999-2024 Gentoo Authors
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EAPI=8
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# get the current value from the yosys makefile...look for ABCREV
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ABC_GIT_COMMIT=0cd90d0d2c5338277d832a1d890bed286486bcf5
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DESCRIPTION="framework for Verilog RTL synthesis"
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HOMEPAGE="http://www.clifford.at/yosys/"
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SRC_URI="
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https://github.com/YosysHQ/${PN}/archive/${P}.tar.gz
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https://github.com/YosysHQ/abc/archive/${ABC_GIT_COMMIT}.tar.gz -> abc-${ABC_GIT_COMMIT}.tar.gz
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"
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S="${WORKDIR}/${PN}-${PN}-${PV}"
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LICENSE="ISC"
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SLOT="0"
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KEYWORDS="~amd64"
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RDEPEND="
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dev-libs/boost
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media-gfx/xdot
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sys-devel/clang
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"
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DEPEND="${RDEPEND}"
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BDEPEND="dev-vcs/git"
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QA_PRESTRIPPED="
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/usr/bin/yosys-filterlib
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/usr/bin/yosys-abc
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"
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src_prepare() {
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mv "${WORKDIR}/abc-${ABC_GIT_COMMIT}" "${S}"/abc || die
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default
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}
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src_install() {
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emake DESTDIR="${D}" PREFIX='/usr' install
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}
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